This disclosure relates to modeling parasitic resistances in semiconductor devices and, more particularly, to a method, system and computer program product for modeling the resistance of a simple or a complex multi-layered conductive component of a semiconductor device.
The parasitic resistance of a conductive component of a semiconductor device (e.g., a gate structure of a field effect transistor (FET), a local interconnect used in a source/drain region of a FET, etc.) will impact the performance of an integrated circuit and, particularly, the performance of very large scale integration (VLSI) circuits, such as ring oscillators, logic gates (e.g., NAND gates, NOR gates, etc.), etc., which incorporates the semiconductor device. For example, the relatively high resistance associated with the flow of current through a local interconnect used in a source/drain region of FET and/or the relatively high resistance associated with the flow of current through the gate structure of that FET can cause the FET to exhibit a relatively slow switching speed. Thus, during semiconductor device design (e.g., during FET design), accurate modeling of the resistances of conductive components of the semiconductor device (e.g., accurate modeling of the resistances of any local interconnect used in the source/drain region of the FET and of the gate structure of the FET) is very important.
Various techniques are well known in the art for modeling the resistances of conductive components in a semiconductor device. Unfortunately, accuracy issues can be associated with such prior art resistance modeling techniques when the conductive component comprises multiple layers of different types of conductive materials and, particularly, when the conductive component has a complex three-dimensional geometry. Specifically, in the case of a gate structure with multiple layers of different types of conductive materials (e.g., as seen in high-K metal-gate FETs, including planar FETs and multi-gate non-planar FETs (MUGFETS), such as double-gate non-planar FETs, also referred to herein as fin-type FETs (FINFETs), and tri-gate non-planar FETs), the prior art gate resistance modeling techniques do not provide accurate results because they do not account for the different types of conductive materials within the gate structure and the complex three-dimensional geometry of the gate structure. Similar accuracy issues can be associated with modeling the resistance of a multi-layered local interconnect used in the source/drain region of a FET (e.g., in the source/drain region of a high-K metal-gate FET). Therefore, there is a need in the art for a technique that can be used to more accurately model the resistance of a multi-layered conductive component of semiconductor device (e.g., a multi-layered gate structure of a planar FET, a multi-layered gate structure of a non-planar FET, a multi-layered local interconnect used in the source/drain region of a FET, etc.).